ESD in Silicon Integrated Circuits, 2nd Edition

本書では、回路保護に関する様々な方法について検討されており、 VLSI 回路の ESD 回路保護方式についてもカバーされています。回路保護の実装対策としてのガイダンスが提供されており、新しいセクションとして ESD 設計のルール・レイアウトアプローチ・パッケージ効果・回路コンセプトに関する記述が含まれています。デバイス帯電モデル (Charged Device Model) のテスト方法について論評され、回路保護に必要とされる設計要求事項についても評価されています。

Preface

1. Introduction
   Background
   The ESD Problem
   Protecting against ESD
   Outline of the Book
2. ESD Phenomenon
   Introduction
   Electrostatic Voltage
   Discharge
   ESD Stress Models
3. Test Methods
   Introduction
   Human Body Model (HBM)
   Machine Model (MM)
   Charged Device Model (CDM)
   Socket Device Model (SDM)
   Metrology, Calibration, Verification
   Transmission Line Pulsing (TLP)
   Failure Criteria
   Summary
4. Physics and Operation of ESD Protection Circuits Elements
   Introduction
   Resistors
   Diodes
   Transistor Operation
   Transistor Operation Under ESD Conditions
   Electrothermal Effects
   SCR Operation
   Conclusion
5. ESD Protection Circuit Design Concepts and Strategy
   The Qualities of Good ESD Protection
   ESD Protection Design Methods
   Selecting an ESD Strategy
   Summary
6. Design and Layout Requirements
   Introduction
   Thick Field Device
   nMOS Transistors (FPDs)
   Gate-Coupled nMOS (GCNMOS)
   Gate Driven nMOS (GDNMOS)
   SCR Protection Device
   ESD Protection Design Synthesis
   Total Input Protection
   ESD Protection Using Diode-Based Devices
   Power Supply Clamps
   BiPolar and BiCMOS Protection Circuits
   Summary
7. Advanced Protection Design
   Introduction
   PNP Driven nMOS (PDNMOS)
   Substrate Triggered nMOS (STNMOS)
   nMOS Triggered nMOS (NTNMOS)
   ESD for Mixed Voltage I/O
   CDM Protection
   SOI Technology
   High-Voltage Transistors
   BiCMOS Protection
   RF Designs
   General I/O Protection Schemes
   Design/Layout Errors
   Summary
8. Failure Modes, Reliability Issues, and Case Studies
   Introduction
   Failure Mode Analysis
   Reliability and Performance Considerations
   Advanced CMOS Input Protection
   Optimizing the Input Protection Scheme
   Designs for Special Applications
   Process Effects on Input Protection Design
   Total IC Chip Protection
   Power Bus Protection
   Internal Chip ESD Damage
   Stress Dependent ESD Behavior
   Failure Mode Case Studies
   Summary
9. Influence of Processing on ESD
   Introduction
   High Current Behavior
   Cross-Section of a MOS Transistor
   Drain-Source Implant Effects
   p-Well Effects
   n-Well Effects
   Epitaxial Layers and Substrates
   Gate Oxides
   Silicides
   Contacts
   Interconnect and Metalization
   Gate Length Dependencies
   Silicon-On-Insulator (SOI)
   Bipolar Transistors
   Diodes
   Resistors
   Reliability Trade-Offs
   Summary
10. Device Modeling of High Current Effects
    Introduction
    The Physics of ESD Damage
    Thermal (“Second”) Breakdown
    Analytical Models Using the Heat Equation
    Electrothermal Device Simulations
    Conclusions
11. Circuit Simulation Basics, Approaches, and Applications
    Introduction
    Modeling the MOSFET
    Modeling Bipolar Junction Transistors
    Modeling Diffusion Resistors
    Modeling Protection Diodes
    Simulation of Protection Circuits
    Electrothermal Circuit Simulations
    Conclusion
12. Conclusions
    Long-Term Relevance of ESD in Ics
    State-of-the-Art for ESD Protection
    Current Limitations
    Future Issues
13. Index